design.v
module half_adder(sum,carry,a,b);
input a,b;
output sum,carry;
xor (sum,a,b);
and (carry,a,b);
endmodule
module fa(fsum,fcarry,a,b,c);
input a,b,c;
output fsum,fcarry;
wire sum1,carry1,carry2;
half_adder ha1(sum1,carry1,a,b);
half_adder ha2(fsum,carry2,sum1,c);
or(fcarry,carry1,carry2);
endmodule
testbench.v
// Code your testbench here
// or browse Examples
module testbench;
reg a,b,c;
wire fsum,fcarry;
integer i;
fa my( fsum,fcarry,a,b,c);
initial begin
$dumpfile("dump.vcd");
$dumpvars;
#100 $finish;
end
initial
begin
a <= 0;
b <= 0;
c <= 0;
$monitor ("a=%0b b=%0b c=%0b fsum=%0b fcarry=%0b", a, b, c, fsum, fcarry);
for (i=0; i< 8; i= i + 1)
begin
{a, b, c} = i;
#10;
end
end
endmodule