design
// Code your design here
// BEHAVIORAL LEVEL
module full_adder (s,cy,a,b,c);
input a,b,c;
output s,cy;
always @(a or b or c)
case ({a, b, c})
3'b000 : begin s=0; cy=0; end
3'b001 : begin s=1; cy=0; end
3'b010 : begin s=1; cy=0; end
3'b011 : begin s=0; cy=1; end
3'b100 : begin s=1; cy=0; end
3'b101 : begin s=0; cy=1; end
3'b110 : begin s=0; cy=1; end
3'b111 : begin s=1; cy=1; end
endcase
end
endmodule
testbench
// Code your testbench here
// or browse Examples
// Code your testbench here
module testbench;
reg a,b,c;
wire s,cy;
integer i;
full_adder my( s,cy,a,b,c);
initial begin
$dumpfile("dump.vcd");
$dumpvars;
#100 $finish;
end
initial
begin
a <= 0;
b <= 0;
c <= 0;
$monitor ("a=%0b b=%0b c=%0b s=%0b cy=%0b", a, b, c, s, cy);
for (i=0; i< 8; i= i + 1)
begin
{a, b, c} = i;
end
end
endmodule