The output, Q of a “Logic OR Gate” only returns “LOW” again when ALL of its inputs are at a logic level “0”. In other words for a logic OR gate, any “HIGH” input will give a “HIGH”, logic level “1” output.
//gate level module orgate (a, b,y); input a,b; output y; or(y,a,b); endmodule
| //data flow module orgate (a,b,y); input a,b; output y; assign y=a|b; endmodule
| //behavioral module orgate (a, b, y); input a,b; output reg y; always@(a or b)begin if(a==1'b0&b==1'b0)begin y=1'b0; end else y=1'b1; end endmodule |
//testbench module ortest; reg a1, b1; wire y1; orgate ortest ( .a(a1), .b(b1), .y(y1)); initial begin $monitor("a=%d b=%d y=%d",a1, b1, y1); a1 = 1'b0; b1 = 1'b0; #5 a1 = 1'b0; b1 = 1'b1; #10 a1 = 1'b1; b1 = 1'b0; #15 a1 = 1'b1; b1 = 1'b1; end initial begin $dumpfile("dump.vcd"); $dumpvars; #100 $finish; end endmodule | ||