Wallace Tree Encoder using Hierarchy

 Wallace Tree Encoder (Verilog Code)

Now a days in Analog to Digital conversion using, an analog to digital converter (ADC), converts any analog signal into quantifiable data, which makes it easier to process and store, as well as more accurate and reliable by minimizing errors. Wallace tree encoder plays a crucial role and it based on converting thermometer code into binary code in ADC.

Here I7 to I1 are Thermometer Code as Input. B0 to B2 are Binary Output. FA is Full Adder Block. 

using hierarchy. So we will follow Bottom to Up Approach. 
I) Half Adder
II) Full Adder using Half Adder
III) Wallace Tree Encoder(3-Bit) using Full Adder

Now, Implementation of Verilog code for the Wallace Tree Encoder. 

Verilog Code 

//Verilog Code for Wallace Tree Encoder(3-bit)

module HA(s,c,a,b);  // Half Adder Module

input a,b;

output s,c;

assign s = a^b;  // It is XOR of a and b for SUM

assign c = a&b;  // It is AND of a and b for CARRY

endmodule

module FA(s,carry,a,b,c); // Full Adder Module

input a,b,c;

output s,carry;

wire p,q,r;  // Wire Defined for connection between the blocks of Half Adder

HA H1(p,q,a,b); //for applying the value a,b as input and taking the value of p,q as output

HA H2(s,r,p,c);

or(carry,r,q);

endmodule

module WallaceTE_3bit(I,B); //3-bit Wallace Tree Encoder

input [7:1]I; //Vector of Thermometer code 7 input

output [2:0]B; //vector of Binary code 3 Output

wire p,q,r,s; //Wire Defined for connection between the blocks of Full Adder

FA F1(p,q,I[5],I[4],I[6]);//for applying the value i5,i4,i6 as input and taking the value of p,q as output.

FA F2(B[0],t, p,r,I[7]);

FA F3(r,s,I[2],I[1],I[3]);

FA F4(B[1],B[2],q,s,t);

endmodule

Testbench

//Testbench for Wallace Tree Encoder(3-bit)

module WallaceTE_3bit_tb();

reg [7:1]I;

wire [2:0]B;

WallaceTE_3bit insta(I,B); //instantiation with verilog code

initial begin //initilization of input

I=0;

#5;

end

initial begin //defining all combination of input(Thermometer code)

I[7]=0; I[6]=0; I[5]=0; I[4]=0; I[3]=0; I[2]=0; I[1]=1; #5;

I[7]=0; I[6]=0; I[5]=0; I[4]=0; I[3]=0; I[2]=1; I[1]=1; #5;

I[7]=0; I[6]=0; I[5]=0; I[4]=0; I[3]=1; I[2]=1; I[1]=1; #5;

I[7]=0; I[6]=0; I[5]=0; I[4]=1; I[3]=1; I[2]=1; I[1]=1; #5;

I[7]=0; I[6]=0; I[5]=1; I[4]=1; I[3]=1; I[2]=1; I[1]=1; #5;

I[7]=0; I[6]=1; I[5]=1; I[4]=1; I[3]=1; I[2]=1; I[1]=1; #5;

I[7]=1; I[6]=1; I[5]=1; I[4]=1; I[3]=1; I[2]=1; I[1]=1; #5;

end

initial begin //for printing Output

  $monitor("I7=%b,I6=%b, I5=%b, I4=%b, I3=%b, I2=%b, I1=%b, B2=%b, B1=%b, B0=%b", I[7],I[6],I[5],I[4],I[3],I[2],I[1],B[2],B[1],B[0]);

#70; $finish; 

end 

endmodule

Output of Code