Basic:--The 2-to-4 line binary decoder depicted above consists of an array of four AND gates. The 2 binary inputs labelled A and B are decoded into one of 4 outputs, hence the description of 2-to-4 binary decoder. Each output represents one of the minterms of the 2 input variables, (each output = a minterm).
//gate level module decoder24(a,b,y); input a,b; output [0:3]y; wire a1,b1; not n1(a1,a); not n2(b1,b);
and n3(y[0],a1,b1); and n4(y[1],a1,b); and n5(y[2],a,b1); and n6(y[3],a,b); endmodule | //data flow module decoder24(a,b,y); input a,b; output [0:3]y; wire a1,b1; assign a1 = ~a; assign b1 = ~b; assign y[0] = (a1&b1); assign y[1] = (a1&b); assign y[2] = (a&b1); assign y[3] = (a&b); endmodule | //behavioral module decoder24(a,b,y); input en,a,b; output reg [0:3]y; always @(a,b) begin if(a==1'b0 & b==1'b0) y=4'b1000 else if(a==1'b0 & b==1'b1) y=4'b0100; else if(a==1'b1 & b==1'b0) y=4'b0010; else if(a==1 & b==1) y=4'b0001; end endmodule |
//testbench module tb; reg a,b; wire [0:3]y; decoder24 dut(a,b,y); initial begin $monitor("a=%b b=%b y=%b",a,b,y); a=0;b=0;#5 a=0;b=1;#5 a=1;b=0;#5 a=1;b=1;#5 $finish; end endmodule Output:- a=0 b=0 y=1000 | ||