AND Gate using all modeling style

 

AND GATE

The AND gate is a basic digital logic gate that implements logical conjunction (∧) from mathematical logic – AND gate behaves according to the truth table. A HIGH output (1) results only if all the inputs to the AND gate are HIGH (1). If not all inputs to the AND gate are HIGH, LOW output results. The function can be extended to any number of inputs.

 

Andgate.v     // testbench is here   module test; reg x,y; wire z;   and_gate test (.a(x), .b(y), .c(z)); //character after dot(.) is for signal initial begin x=0; y=0; #5 x=0; y=1; #5 x=1; y=0; #5 x=1; y=1; end initial begin $monitor("a=%d b=%d c=%d", x, y, z); $dumpfile("dump.vcd"); $dumpvars; #100 $finish; end endmodule	//Design: And Gate Level   module and_gate (c, a, b); input a, b; output c; and (c, a, b); endmodule
	//Design: And Data Flow   module and_gate (c, a, b); input a, b; output c; assign c= a&b endmodule
	//Design: And Behavioral or Algorithmic Level   module and_gate (c, a, b); input a, b; output reg  c; always @ (a or b) begin if(a == 1 & b == 1) begin c=1; end else c=0; end endmodule

 

 

        Output:                                                                     Graphical Output: