The D flip flop is the most important flip flop from other clocked types. It ensures that at the same time, both the inputs, i.e., S and R, are never equal to 1. The Delay flip-flop is designed using a gated SR flip-flop with an inverter connected between the inputs allowing for a single input D(Data).
This single data input, which is labeled as "D" used in place of the "Set" input and for the complementary "Reset" input, the inverter is used. Thus, the level-sensitive D-type or D flip flop is constructed from a level-sensitive SR flip flop.
module D_FF(Q,Qb,D,clk);
input D,clk;
output reg Q,Qb;
always@(D,clk)
begin
if(clk==1)
Q=D;
else
Q=~D;
if(clk==1)
Qb=~Q;
else
Qb=Q;
end
endmodule
testbench code :
module D_FF_tb;
reg D,clk;
wire Q,Qb;
D_FF flipflop(Q,Qb,D,clk);
initial
begin
$dumpfile("dump.vcd");
$dumpvars;
$monitor("clk=%b, D=%b, Q=%b, Qb=%b",clk,D,Q,Qb);
clk=0; D=1;
#5 clk=1; D=0;
#5 clk=1; D=1;
#5 $finish;
end
endmodule