world of verilog

2-4 Decoder using all modeling style.

Basic:-- The 2-to-4 line binary decoder depicted above consists of  an array of four AND gates.   The 2 binary inputs labelled …

bysimple verilog -November 30, 2022

OR GATE Verilog Using All Modeling style

The output, Q of a “Logic OR Gate” only returns “LOW” again when  ALL  of its inputs are at a logic level “0”. In other words …

bysimple verilog -November 29, 2022

AND Gate using all modeling style

AND GATE The  AND gate  is a basic digital  l ogic gate  that implements  logical conjunction  (∧) from  mathematical logic  –…

byFounder : Vimal Mer -November 29, 2022

D Flip Flop

The D flip flop is the most important flip flop from other clocked types. It ensures that at the same time, both the inputs, i…

bykamleshkumar -November 29, 2022

4x1 Mux Using Ternary operator

Multiplexer   is a combinational circuit that has maximum of 2 n   data inputs, ‘n’ selection lines and single output line. One …

byFounder : Rajat sahu -November 28, 2022